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Dr. U. Jagadish's Project and Research highlights at ORNL
2004-2006 Lead firmware designer for a low power, embedded microchip
controller (PIC) based custom paging system with RFID. It was designed with Post
Office Code Standardization Advisory Group (POCSAG) decoding and RFID for
Criticality Annunciation System (CAS) alerts. Project resulted in the prestigious
2005 Y-12 Government Use Award with a patent being filed.
2003-2005 Co-lead of a novel sensor system with wireless communication.
System was for detecting hostile impacts in oil tanks for homeland security using
vibration detectors and transmission in the GSM band. Successful completion of
the project has resulted in a patent being filed.
2001-2003 Lead designer of the RF transceiver node with commercial off the
shelf (COTS) components in a down-hole distributed, tethered, smart sensor node
system used in the oil industry. These nodes had an 881.5/ 836.5 MHz. duplexer,
LNA, Mixer, IF filter, AGC, modulator/ demodulator and power amplifiers. Designed
an RF mixer circuit in the 0.5μ CMOS SOI peregrine technology for the subsequent
ASIC version.
2002-2003 Lead interface designer of the mechanical front end interface for a
High Temperature Segmented Silicon Alpha Detector. It consists of ceramic layers
to form electrical interconnects between the pixel detector element and the readout
pins, using a novel technique of ultra-thin ceramic disks (10 mil thickness) with
etched circuits sandwiched together and mechanically assembled using 0.5mm
diameter fuzz-button interconnects.
2002-2003 Lead layout designer of an RF mixer ASIC in Slicon-Germanium
(SiGe) technology as part of an Office of Industrial Technology (OIT) initiative. The
mixer was designed to work as a QPTT demodulator for high frequencies. It was
tested with signals of 2.94 GHz. and 2.8 GHz to extract the 140 MHz Intermediate
Frequency (IF) signal successfully.
2002-2003 Lead designer for the receiver section of a thermometry scheme to
measure high temperatures in the harsh environment of a nuclear power plant
using the Johnson Noise Thermometry (JNT) techniques. Designed, implemented
and tested a receiver with differential amplifiers and Sallen-key filters customized
for the noise measurement channels. The PCI 9812 - a 4-channel, 20 MHZ ADC
interface board with DSP and Labview was used to design a General User
Interface. Also designed a robust mechanical housing and a user manual for the
entire system test.
2001- 2002 Lead ASIC engineer of a custom front-end ASIC for a mixed signal
chip for a pixilated cold neutron detector which could be used for cold neutron
imaging and x-ray imaging. Designed the shaper stages, gain, discriminator, and
a voltage to current back end stage that followed the preamplifier. Also designed
the test board, and devised an interactive test program in C to load the serial
registers and read back values. The chip was fabricated in 0.5 micron AMI
technology.
2000-2002 Co-lead of the hardware design of smart sensor nodes for NASA-
MSFC and established the hardware needed for inter nodal communication in a
tethered system and was responsible for the transceiver design. Was part of the
team that designed the architecture for load distribution in Scalable Fault Tolerant
Intelligent Networks for Transducers (SFINX). The project was a joint venture
between NASA-MSFC, Draper Labs and ORNL.
2001 - 2003 Part of the team that designed an ASIC front end for an Avalanche
Photodiode array Detector (APD) which was part of the SOlar Neutron TRACking
experiment (SONTRAC). Was responsible for integrating all the required circuits
onto the ASIC floor plan and simulating the entire system. The four-channel
prototype ASIC was fabricated using the 0.35 micron TSMC.
1995-1996 Lead ASIC integration designer for a 64 channel front-end ASIC in
0.7u CMOS technology for the Relativistic Heavy Ion Collider (RHIC) physics
experiment called PHOBOS at Brookhaven, NY. The 64 channel version was based
on the success of a 16 channel version. Each channel had protection circuitry,
preamplifier, test charge generator, chip reset circuitry, and individual channel
resets, serial chains, bias elements and serial readout back-end. This project was
a joint venture with the Laboratory of Nuclear Science at Massachusetts Institute of
Technology (MIT).
1999-2000 Lead ASIC chip layout designer of a custom mixed-signal ASIC for
Physical Sciences Inc., Andover, MA (PSI). The ASIC had a core comprising of 16
dual-polarity preamplifier-shaper-discriminator channels and a north harness
comprising of the DACs to set different values and a south harness that had the
bias elements for biasing the different components of the channel. The chip had 5
different gain selects, an overload detector, and 5 adjustable time constants
corresponding to signal peaks of 500ns, 1us, 2us, 4us and 8us. The chip was
fabricated in the ORBIT 1.2 micron n-well CMOS process.
1996-2000 Lead ASIC layout engineer of a custom front end ASIC called the
TGLD, a charge readout chip for the PHENIX Pad Chamber (PC) subsystem at
Brookhaven National Laboratory’s Relativistic Heavy Ion Collider (RHIC) in Upton,
NY. Each ASIC channel comprised of a test pulse circuit, charge sensitive amplifier,
gain, leading edge discriminator, one-shot circuit and a current switch. The chip
was done in 1.2μ CMOS n-well process. The PC subsystem accounts for 207,360
of the approximately 600,000 detector channels in PHENIX, with each channel
being serviced by the TGLD chips. The experiment is still running today (2006) and
giving excellent results that help in understanding basic physics better. Was
awarded the Oak Ridge National Laboratory’s Significant Event Award in 1997 for
my work in this project. The PHENIX experiment is a collaboration between 51
institutions in 11 countries.
1994-1997 Worked on the Nuclear Reactor Protection System team and helped
design the FPGA based control system for monitoring the physical parameters and
running the health algorithm of a Nuclear Power plant. This was a new approach
for reactor protection and safety system signal processing and voting logic. The
software logic was implemented for pressure and temperature channels and trip
conditions for a typical pressurized water reactor. The FPGA was implemented in
the fuse logic type one-time programmable Actel devices.
1994-1995 Was a team member of the Nuclear Weapons Identification System
(NWIS) program whose aim was to provide a portable, accurate and sensitive
detector to identify nuclear weapons around the world. Designed the front end
electronics with discrete components including Constant Fraction Discriminators
(CFD) and precision timing circuits. These circuits were used in the
instrumentation attached to nuclear radiation detector heads.
2004-2006 Lead firmware designer for a low power, embedded microchip
controller (PIC) based custom paging system with RFID. It was designed with Post
Office Code Standardization Advisory Group (POCSAG) decoding and RFID for
Criticality Annunciation System (CAS) alerts. Project resulted in the prestigious
2005 Y-12 Government Use Award with a patent being filed.
2003-2005 Co-lead of a novel sensor system with wireless communication.
System was for detecting hostile impacts in oil tanks for homeland security using
vibration detectors and transmission in the GSM band. Successful completion of
the project has resulted in a patent being filed.
2001-2003 Lead designer of the RF transceiver node with commercial off the
shelf (COTS) components in a down-hole distributed, tethered, smart sensor node
system used in the oil industry. These nodes had an 881.5/ 836.5 MHz. duplexer,
LNA, Mixer, IF filter, AGC, modulator/ demodulator and power amplifiers. Designed
an RF mixer circuit in the 0.5μ CMOS SOI peregrine technology for the subsequent
ASIC version.
2002-2003 Lead interface designer of the mechanical front end interface for a
High Temperature Segmented Silicon Alpha Detector. It consists of ceramic layers
to form electrical interconnects between the pixel detector element and the readout
pins, using a novel technique of ultra-thin ceramic disks (10 mil thickness) with
etched circuits sandwiched together and mechanically assembled using 0.5mm
diameter fuzz-button interconnects.
2002-2003 Lead layout designer of an RF mixer ASIC in Slicon-Germanium
(SiGe) technology as part of an Office of Industrial Technology (OIT) initiative. The
mixer was designed to work as a QPTT demodulator for high frequencies. It was
tested with signals of 2.94 GHz. and 2.8 GHz to extract the 140 MHz Intermediate
Frequency (IF) signal successfully.
2002-2003 Lead designer for the receiver section of a thermometry scheme to
measure high temperatures in the harsh environment of a nuclear power plant
using the Johnson Noise Thermometry (JNT) techniques. Designed, implemented
and tested a receiver with differential amplifiers and Sallen-key filters customized
for the noise measurement channels. The PCI 9812 - a 4-channel, 20 MHZ ADC
interface board with DSP and Labview was used to design a General User
Interface. Also designed a robust mechanical housing and a user manual for the
entire system test.
2001- 2002 Lead ASIC engineer of a custom front-end ASIC for a mixed signal
chip for a pixilated cold neutron detector which could be used for cold neutron
imaging and x-ray imaging. Designed the shaper stages, gain, discriminator, and
a voltage to current back end stage that followed the preamplifier. Also designed
the test board, and devised an interactive test program in C to load the serial
registers and read back values. The chip was fabricated in 0.5 micron AMI
technology.
2000-2002 Co-lead of the hardware design of smart sensor nodes for NASA-
MSFC and established the hardware needed for inter nodal communication in a
tethered system and was responsible for the transceiver design. Was part of the
team that designed the architecture for load distribution in Scalable Fault Tolerant
Intelligent Networks for Transducers (SFINX). The project was a joint venture
between NASA-MSFC, Draper Labs and ORNL.
2001 - 2003 Part of the team that designed an ASIC front end for an Avalanche
Photodiode array Detector (APD) which was part of the SOlar Neutron TRACking
experiment (SONTRAC). Was responsible for integrating all the required circuits
onto the ASIC floor plan and simulating the entire system. The four-channel
prototype ASIC was fabricated using the 0.35 micron TSMC.
1995-1996 Lead ASIC integration designer for a 64 channel front-end ASIC in
0.7u CMOS technology for the Relativistic Heavy Ion Collider (RHIC) physics
experiment called PHOBOS at Brookhaven, NY. The 64 channel version was based
on the success of a 16 channel version. Each channel had protection circuitry,
preamplifier, test charge generator, chip reset circuitry, and individual channel
resets, serial chains, bias elements and serial readout back-end. This project was
a joint venture with the Laboratory of Nuclear Science at Massachusetts Institute of
Technology (MIT).
1999-2000 Lead ASIC chip layout designer of a custom mixed-signal ASIC for
Physical Sciences Inc., Andover, MA (PSI). The ASIC had a core comprising of 16
dual-polarity preamplifier-shaper-discriminator channels and a north harness
comprising of the DACs to set different values and a south harness that had the
bias elements for biasing the different components of the channel. The chip had 5
different gain selects, an overload detector, and 5 adjustable time constants
corresponding to signal peaks of 500ns, 1us, 2us, 4us and 8us. The chip was
fabricated in the ORBIT 1.2 micron n-well CMOS process.
1996-2000 Lead ASIC layout engineer of a custom front end ASIC called the
TGLD, a charge readout chip for the PHENIX Pad Chamber (PC) subsystem at
Brookhaven National Laboratory’s Relativistic Heavy Ion Collider (RHIC) in Upton,
NY. Each ASIC channel comprised of a test pulse circuit, charge sensitive amplifier,
gain, leading edge discriminator, one-shot circuit and a current switch. The chip
was done in 1.2μ CMOS n-well process. The PC subsystem accounts for 207,360
of the approximately 600,000 detector channels in PHENIX, with each channel
being serviced by the TGLD chips. The experiment is still running today (2006) and
giving excellent results that help in understanding basic physics better. Was
awarded the Oak Ridge National Laboratory’s Significant Event Award in 1997 for
my work in this project. The PHENIX experiment is a collaboration between 51
institutions in 11 countries.
1994-1997 Worked on the Nuclear Reactor Protection System team and helped
design the FPGA based control system for monitoring the physical parameters and
running the health algorithm of a Nuclear Power plant. This was a new approach
for reactor protection and safety system signal processing and voting logic. The
software logic was implemented for pressure and temperature channels and trip
conditions for a typical pressurized water reactor. The FPGA was implemented in
the fuse logic type one-time programmable Actel devices.
1994-1995 Was a team member of the Nuclear Weapons Identification System
(NWIS) program whose aim was to provide a portable, accurate and sensitive
detector to identify nuclear weapons around the world. Designed the front end
electronics with discrete components including Constant Fraction Discriminators
(CFD) and precision timing circuits. These circuits were used in the
instrumentation attached to nuclear radiation detector heads.
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